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Formal Verification of DSP VLSI Architectures: A Tutorial

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dc.contributor.advisor Elleithy, Khaled M. en_US
dc.contributor.author Elleithy, Khaled M. en_US
dc.contributor.author Al-Humaigani, Muhammad A. en_US
dc.date.accessioned 2014-07-16T16:58:00Z
dc.date.available 2014-07-16T16:58:00Z
dc.date.issued 1994-08-03 en_US
dc.identifier.other 329b5058-0de8-73db-48f2-e82787698e71 en_US
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/793
dc.description.abstract In this tutorial paper the area of formal verification of DSP VLSI architectures is presented. The paper discuses the following topics: production systems, formal logic, the equational approach, and the signal flow graph approach. Each approach is explained using one or more of the current available systems. en_US
dc.description.uri http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=519255&tag=1 en_US
dc.publisher IEEE en_US
dc.title Formal Verification of DSP VLSI Architectures: A Tutorial en_US
dc.type Article en_US
dc.event.location Lafayette, Louisiana USA en_US
dc.event.name 37th Midwest Symposium on Circuits and Systems en_US

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