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Design Of A Cell Library For Formal High Level Synthesis

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dc.contributor.advisor Elleithy, Khaled M. en_US
dc.contributor.author Elleithy, Khaled M. en_US
dc.contributor.author Sait, Sadiq M. en_US
dc.contributor.author Hasan, Masud-ul en_US
dc.date.accessioned 2014-07-16T16:57:53Z
dc.date.available 2014-07-16T16:57:53Z
dc.date.issued 1994-04 en_US
dc.identifier.other 8c2f6222-51e0-48de-d00f-88f5c0231407 en_US
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/790
dc.description.abstract In this paper we present a complete design and implementation of a CMOS cell library which supports a formal high level synthesis framework. The library contains the logic level models and VLSI layouts of all primitive functions of the Realization Specification Language (RSL) [l] as well as some commonly used functions which are also built using these basic functions. Modular design methodology is employed to support the expandibility of the basic cells. Example of a formal matrix-matrix multiplier is presented to illustrate the application of the cell library. en_US
dc.description.uri http://ieeexplore.ieee.org.libproxy.bridgeport.edu:9000/stamp/stamp.jsp?tp=&arnumber=380842 en_US
dc.title Design Of A Cell Library For Formal High Level Synthesis en_US
dc.type Article en_US
dc.event.name Mediterranean Electrontecnical Conference Melecon 93 en_US


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