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A Rule-based Approach for High Speed Adders Design Verification

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dc.contributor.advisor Elleithy, Khaled M. en_US
dc.contributor.author Elleithy, Khaled M. en_US
dc.contributor.author Aref, Mostafa A. en_US
dc.date.accessioned 2014-07-16T16:57:40Z
dc.date.available 2014-07-16T16:57:40Z
dc.date.issued 1994-08-03 en_US
dc.identifier.other 02e95e98-a0ac-0802-0bb7-7b2163a4dd9d en_US
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/784
dc.description.abstract In this paper, a rule-based framework for formal hardware verification is presented. The PROVER system (PROduction system for hardware VERification) is implemented using CLIPS (C Language Integrated Production System). The environment supports verification at different levels of hardware specification. The rule-based framework has been tested on the design of high speed adders. en_US
dc.description.uri http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=519238&tag=1 en_US
dc.publisher IEEE en_US
dc.subject Algorithms analysis en_US
dc.subject Digital integrated circuit design en_US
dc.subject Electrical engineering en_US
dc.subject Engineering en_US
dc.title A Rule-based Approach for High Speed Adders Design Verification en_US
dc.type Article en_US
dc.event.location Lafayette, Louisiana, USA en_US
dc.event.name 1993 37th Midwest Symposium on Circuits and Systems en_US


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