Abstract:
Low power VLSI has become a very hot area due to the rapid increase in energy cost and wide applications of mobile electronics. Various techniques can be used to reduce the power consumption of VLSI circuits. In this paper, a novel low-power 32-bit comparator using pass transistor and logic shut-down technique is proposed. The comparator will first compare the higher bits of the input patterns. Whenever a decision can be made, the comparison logic for the lower bits will be shut down to save power. The lower bits are compared only when a decision cannot be made from the higher bits. In this way, the unnecessary comparisons are avoided and the power savings can be maximized. Pass transistor logic is also utilized in the comparator design to further reduce the transistor count so that the power consumption can be further reduced compared to CMOS logic. Other comparators are also compared. The schematic design for proposed comparator is designed with PSPSICE. The netlists are extracted and fed to PSPICE for power analysis. An auxiliary power measurement circuitry is introduced to measure the power consumption of the circuits in a smart way. Simulation results show that using pass-transistor and logic shut down techniques can significantly reduce the consumption of the transistor and the power, furthermore, the shrinking signal path are introduced for delay improvement.
