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e(logN) Architectures For RNS Arithmetic Decoding

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dc.contributor.advisor Elleithy, Khaled M. en_US
dc.contributor.author Elleithy, Khaled M. en_US
dc.contributor.author Bayoumi, Magdy A. en_US
dc.contributor.author Lee, K. P. en_US
dc.date.accessioned 2014-07-16T16:54:37Z
dc.date.available 2014-07-16T16:54:37Z
dc.date.issued 1989-09-06 en_US
dc.identifier.other 3281ee53-afe1-742b-3a8e-a64b99b4f68f en_US
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/728
dc.description.abstract Decoding in Residue Number System (RNS) based architectures can be a bottleneck. A high speed and flexible modulo decoder is an essential computational element to maintain the advantages of RNS. In this paper, a fast and flexible modulo decoder, based on the Chinese Remainder Theorem (CRT) is presented. It decodes a set of residues into its equivalent representation in either unsigned magnitude or 2s complement binary number system. Two different architectures are analyzed; the first one is based on using Carry Save Adders(CSA), while, the other is based on utilizing a modified structure of Carry Save Adders(MCSA). Both architectures are modular and are based on simple cells, which leads to efficient VLSI implementation. The proposed decoder is fast, it has a time complexity of e( IogN). en_US
dc.description.uri http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=72827 en_US
dc.subject Computation theory en_US
dc.subject Computer science en_US
dc.subject Mathematics en_US
dc.subject Operation research en_US
dc.title e(logN) Architectures For RNS Arithmetic Decoding en_US
dc.type Article en_US
dc.event.location Santa Monica, CA en_US
dc.event.name 1988 The 9th Symposium on Computer Arithmetic en_US

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