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Reverse Engineering Of VLSI Chips: A Roadmap

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dc.contributor.advisor Elleithy, Khaled M. en_US
dc.contributor.advisor Sobh, Tarek M. en_US
dc.contributor.author Sobh, Tarek M. en_US
dc.contributor.author Elleithy, Khaled M. en_US
dc.contributor.author Patel, Sarosh en_US
dc.date.accessioned 2014-07-16T16:36:39Z
dc.date.available 2014-07-16T16:36:39Z
dc.date.issued 2007 en_US
dc.identifier.citation T. M. Sobh, K. M. Elleithy, S. Patel, "Reverse Engineering Of VLSI Chips: A Roadmap," Journal of Engineering and Applied Sciences, vol. 2, no. 2, 2007.
dc.identifier.other 86c63137-c7d8-8209-ed9e-53eef6db0b37 en_US
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/498
dc.description The reverse engineering process for VLSI chips is a complex operation that can cost from $10,000 for the simplest chips to hundreds of thousands of dollars for complex chips. In this study, we present an overview of the process of reverse engineering VLSI en_US
dc.description.uri http://docsdrive.com/pdfs/medwelljournals/jeasci/2007/290-298.pdf en_US
dc.publisher Medwell Journals en_US
dc.subject Architecture en_US
dc.subject Models en_US
dc.subject Very-large-scale integration (VLSI) en_US
dc.subject Multilevel structures geometric properties en_US
dc.subject Benchmark examples en_US
dc.subject Neurology en_US
dc.subject Computer architecture en_US
dc.subject Computer engineering en_US
dc.subject Computer science en_US
dc.subject Engineering en_US
dc.subject Very-large-scale integration (VLSI) design en_US
dc.title Reverse Engineering Of VLSI Chips: A Roadmap en_US
dc.type Article en_US
dc.publication.issue 2 en_US
dc.publication.name Journal of Engineering and Applied Sciences en_US
dc.publication.volume 2 en_US
dc.notes 11/23/11-Need permission from Medwell Journals en_US


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