Parallel Sparse-Matrix Solution For Direct Circuit Simulation On A Transputer Array

Abstract

Sparse-matrix solution is a dominant part of execution time in simulating VLSI circuits by a detailed simulation program such as SPICE. The paper develops a parallel-block partitionable sparse-matrix-solution algorithm which exploits sparsity at the matrix block level as well as within a nonzero block. An efficient mapping scheme to assign different matrix blocks to processors is developed which maximizes concurrency and minimizes communication between processors. Associated reordering and efficient sparse storage schemes are also developed. Implementation of this parallel algorithm is carried out on a transputer processor array which plugs into a PC bus. The sparse matrix solver is tested on matrices generated from a transistor-level expansion of ISCAS-85 benchmark logic circuits. Good acceleration is obtained for all benchmark matrices up to the number of transputers available.