UB ScholarWorks

Fast And Flexible Architectures For Rns Arithmetic Decoding

Show simple item record

dc.contributor.advisor Elleithy, Khaled M. en_US
dc.contributor.author Elleithy, Khaled M. en_US
dc.contributor.author Bayoumi, Magdy A. en_US
dc.date.accessioned 2014-07-16T16:35:14Z
dc.date.available 2014-07-16T16:35:14Z
dc.date.issued 1992-04 en_US
dc.identifier.citation K. M. Elleithy, M. A. Bayoumi, "Fast And Flexible Architectures For Rns Arithmetic Decoding," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 39, no. 4, Apr. 1992.
dc.identifier.other df2b91f3-bb1f-16c3-2eb5-d82b58155b0c en_US
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/476
dc.description.abstract An implementation of a fast and flexible residue decoder for residue number system (RNS)-based architectures is proposed. The decoder is based on the Chinese Remainder Theorem (CRT). It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders (CSA's), while the other is based on utilizing modulo adders (MA). The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of O(log N ) ( N is the number of moduli). en_US
dc.description.uri http://ieeexplore.ieee.org.libproxy.bridgeport.edu/stamp/stamp.jsp?tp=&arnumber=136572 en_US
dc.publisher IEEE en_US
dc.subject Residue number system en_US
dc.subject Chinese remainder theorem en_US
dc.subject Modulo adder en_US
dc.subject Carry-save adder en_US
dc.subject Residue decoding en_US
dc.subject Finite field algorithm en_US
dc.subject Appraisal en_US
dc.title Fast And Flexible Architectures For Rns Arithmetic Decoding en_US
dc.type Article en_US
dc.publication.issue 4 en_US
dc.publication.name IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing en_US
dc.publication.volume 39 en_US


Files in this item

Files Size Format View

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record

Search ScholarWorks


Advanced Search

Browse

My Account