Abstract:
Quantum cellular automaton technology (QCA) is a newly-developed technology for next-generation nanoelectronics. It results in high device density, ultra-fast speed and almost zero power dissipation. Multiplier is an important unit in microprocessor design. Traditional N-bit array multiplier consists of N*N adder units and results in large circuit area. In this poster, a novel area-efficient self-cycling architecture for N-bit multiplier is proposed. It ingeniously utilizes the inherent pipeline feature of QCA clock zones to convert the array multiplication into a serial-in serial-out process. In this way, the N-bit multiplier can be implemented with a single (instead of N*N) adder unit, which leads to significant area saving. The proposed self-cycling architecture can be extended to other N-bit QCA circuits as well. It is especially suitable for area-critical QCA circuit design where serial output can be accepted.
