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An 8-bit Low Power Energy Recovery Full Adder Design

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dc.contributor.author Zhang, Xuan
dc.contributor.author Liu, Zhentao
dc.contributor.author Zhang, Linfeng
dc.contributor.author Xiong, Xingguo
dc.date.accessioned 2017-04-07T20:06:58Z
dc.date.available 2017-04-07T20:06:58Z
dc.date.issued 2017-03-24
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/1938
dc.description.abstract With the development of wireless communication and portable electronic products, circuit power consumption has become the critical bottleneck of the VLSI design. Among the low power VLSI designs, adiabatic circuit shows a promising future and has been studied by many researchers. As a newly emerged low power technique, adiabatic circuits can be implemented with different architectures such as PAL, 2N-2N2P, ECRL, and CAL, etc. They all lead to significant power saving. In this paper, we implemented true single-phase energy-recovering logic (TSEL) in PSPICE to build a 8-bit low power full adder. In order to verify the power saving of the adiabatic design, a traditional 8-bit static CMOS full adder is also designed in PSPICE for reference. PSPICE power simulation is used to simulate the power consumption of both full adder designs for the same given input pattern sequence. PSPICE power simulation result shows that TSEL full adder lead to effective power saving compared to conventional CMOS full adder. The adiabatic design also shows good potential to be used in high speed circuit design. en_US
dc.language.iso en_US en_US
dc.subject Complementary metal–oxide semiconductor (CMOS) en_US
dc.subject Low power consumption en_US
dc.subject Very-large-scale integration (VLSI) en_US
dc.title An 8-bit Low Power Energy Recovery Full Adder Design en_US
dc.type Presentation en_US
dc.institute.department School of Engineering en_US
dc.institute.name University of Bridgeport en_US
dc.event.location Bridgeport, CT en_US
dc.event.name Faculty Research Day en_US


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