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RISC Architecture Using Gallium Arsenide

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dc.contributor.author Oza, Hitaishu Yadunandan
dc.date.accessioned 2015-11-20T16:34:12Z
dc.date.available 2015-11-20T16:34:12Z
dc.date.issued 1989
dc.identifier.citation H.Y. Oza, "RISC Architecture Using Gallium Arsenide", M.S. dissertation, Dept. of Engineering, Univ. of Bridgeport, Bridgeport, CT, 1989. en_US
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/1351
dc.description This thesis is being archived as a Digitized Shelf Copy for campus access to current students and staff only. We currently cannot provide this open access without the author's permission. If you are the author of this work and desire to provide it open access or wish access removed, please contact the Wahlstrom Library to discuss permission. en_US
dc.description.abstract The Gallium Arsenide (GaAs) chips have many advantages over silicon chips as far as computer design is concerned. The most important advantage is its relatively less execution time. To implement GaAs chips in computers the 'Reduced Instruction Set Computer (RISC)' is the ideal choice. The main reason behind using RISC is that it uses simple instructions, which needs simple decoding circuits. Therefore, these decoding circuits need fewer number of transistors to implement them. Since GaAs chips have fewer number of transistors RISC is the ideal choice. Moreover, if RISC is used then the execution of the instructions would be faster. These and other advantages of RISC are explained in various parts of this thesis. This thesis also discuses the disadvantages of GaAs and RISC architecture. Moreover, this thesis explains GaAs RISC architectures developed by McDonnell Douglas Astronautics Company, Control Data Corporation & Texas Instruments, and RCA Corporation & Purdue University. All the above mentioned architectures are 32-bit architectures and they are the best architectures available with current GaAs technology. Moreover, all the above mentioned companies are given contracts by DARPA to develop 32-bit architectures using GaAs technology. In addition, an attempt is made to explain GaAs architecture design using 'Wafer Scale Integration (WSI)'. In this thesis memory design, execution unit design, register design and control unit design for GaAs RISC is discussed. The GaAs chips also affects the design of compilers. Therefore it is also covered in this thesis. The comparison of GaAs and Si is also given here. en_US
dc.language.iso en_US en_US
dc.subject Gallium Arsenide (GaAs) chips en_US
dc.subject Silicon chips en_US
dc.subject Reduced instruction set computing (RISC) en_US
dc.subject Circuits en_US
dc.title RISC Architecture Using Gallium Arsenide en_US
dc.type Thesis en_US
dc.institute.department School of Engineering en_US
dc.institute.name University of Bridgeport en_US

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