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Implementation of a CMOS Wallace-tree Multiplier

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dc.contributor.author Li, Xiaoping
dc.contributor.author Xiong, Xingguo
dc.contributor.author Bajwa, Hassan
dc.contributor.author Patra, Prabir
dc.date.accessioned 2015-07-11T18:09:22Z
dc.date.available 2015-07-11T18:09:22Z
dc.date.issued 2009-04
dc.identifier.uri https://scholarworks.bridgeport.edu/xmlui/handle/123456789/1256
dc.description © ASEE 2009 en_US
dc.description.abstract As slow and expensive operation units, multipliers are often the bottleneck limiting the overall performance of many computational VLSI circuits. Various CMOS multiplier architectures are available, such as the array multiplier, carry-save multiplier, and Wallace-tree multiplier. Wallace-tree multiplier has been a very popular design due to its fast speed, ease for modularization and fabrication. In this paper, the design and simulation of an 8-bit Wallace-tree multiplier with PSPICE is proposed. In order for comparison, an 8-bit CMOS array multiplier is also designed. The worst-case delay of both multiplier architectures are extracted and Wallace-tree multiplier demonstrates significant speed enhancement compared to CMOS array multiplier. Some efforts are made to further improve the performance of Wallace-tree multiplier. The revision in the circuit structure demonstrates effective speed improvement for the Wallace-tree multiplier. en_US
dc.language.iso en_US en_US
dc.publisher ASEE en_US
dc.subject Complementary metal–oxide semiconductor (CMOS) en_US
dc.subject Very-large-scale integration (VLSI) circuits en_US
dc.subject Wallace-tree multiplier en_US
dc.title Implementation of a CMOS Wallace-tree Multiplier en_US
dc.type Article en_US
dc.event.location Bridgeport, CT en_US
dc.event.name 2009 Northeast ASEE Conference en_US

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