A Noise Immune Technique to Suppress the Temporal Noise for Wide Dynamic Range CMOS Sensors
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Authors
Babu Sukhavasi, Suparshya
Babu Sukhavasi, Susrutha
Issue Date
2019-03-29
Type
Other
Language
en_US
Keywords
Complementary metal–oxide semiconductor (CMOS) , Noise suppression , Sensor
Alternative Title
Abstract
A CMOS image sensor architecture is presented that uses an extra level of parallelism and thermal and 1/f noise suppression techniques to achieve both low-light detection and a high frame rate. By adding the row-parallel readout ADCs, the conversion speed is improved by more than twice compared to the conventional top-bottom parallel ADC structure. The thermal and 1/f noise is reduced by combining the intrinsic oversampling of the incremental sigma-delta ADCs and the 1/f noise suppression through the source-follower inversion-to accumulation method. The chip contains 164 pads, including 24 LVDS drivers. Rows and columns follow the same readout paths. The pixels are surrounded by the pixel-bias circuits and by the switches for cycling the source follower of the pixels from inversion to accumulation for low-frequency noise reduction. The ADC is the key building block of the designed imager.