Systolic Arithmetic Architectures
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Authors
Elleithy, Khaled M.
Issue Date
1992-01-04
Type
Article
Language
Keywords
Computer aided manufacturing , Computer science , Engineering , Manufacturing technologies , Mechanical engineering
Alternative Title
Abstract
In this paper parallelism on the algorithmic, architectural, and arithmetic levels is exploited in the design of a Residue Number System (RNS) based architecture. The architecture is based on modulo processors. Each modulo processor is implemented by two dimensional systolic array composed of very simple cells. The decoding stage is implemented using a 2-D array, too. The decoding bottleneck is eliminated. The whole architecture is pipelined which lead to high throughput rate.