An 8-bit Low Power Energy Recovery Full Adder Design
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Authors
Zhang, Xuan
Liu, Zhentao
Zhang, Linfeng
Xiong, Xingguo
Issue Date
2017-03-24
Type
Presentation
Language
en_US
Keywords
Complementary metal–oxide semiconductor (CMOS) , Low power consumption , Very-large-scale integration (VLSI)
Alternative Title
Abstract
With the development of wireless communication and portable electronic products, circuit power consumption has become the critical bottleneck of the VLSI design. Among the low power VLSI designs, adiabatic circuit shows a promising future and has been studied by many researchers. As a newly emerged low power technique, adiabatic circuits can be implemented with different architectures such as PAL, 2N-2N2P, ECRL, and CAL, etc. They all lead to significant power saving. In this paper, we implemented true single-phase energy-recovering logic (TSEL) in PSPICE to build a 8-bit low power full adder. In order to verify the power saving of the adiabatic design, a traditional 8-bit static CMOS full adder is also designed in PSPICE for reference. PSPICE power simulation is used to simulate the power consumption of both full adder designs for the same given input pattern sequence. PSPICE power simulation result shows that TSEL full adder lead to effective power saving compared to conventional CMOS full adder. The adiabatic design also shows good potential to be used in high speed circuit design.