Design and Simulation of Full-Custom 8-bit ALU
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Authors
Bishwokarma, Rajiv
Ibrahim, Mina Gaber, Wahba
Xiong, Xingguo (Advisor)
Issue Date
2023-03-24
Type
Other
Language
en_US
Keywords
Arithmetic Logic Unit (ALU) , Custom CMOS Design , Layout Design , PSPICE Simulation , Open-Source Hardware
Alternative Title
Abstract
In this poster, the design, simulation, and physical layout implementation of a fullcustom 8-bit Arithmetic Logic Unit (ALU) is presented. The ALU is designed to operate for 6 modes of functions. Different logic families including static CMOS, transmissiongate based design, MUX-based design are incorporated in this custom design to improve its performance. Carry-lookahead adder (CLA) is used for adder implementation for fast computations. One 8x1 multiplexer (MUX) was designed using 7 2x1 multiplexers and each of these 2x1 MUX were designed using a transmission gate logic. Each instruction was successfully tested by using a custom test circuit with various input patterns. The complete ALU was carried out using the recently opensourced GlobalFoundries 180 nanometer 7-track standard cell library. The 8-bit ALU is designed, and it is verified to perform the correct functions as designed.
Description
UB Rise 2023
Department of Computer Engineering
School of Engineering