Design Of A Cell Library For Formal High Level Synthesis
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Authors
Elleithy, Khaled M.
Sait, Sadiq M.
Hasan, Masud-ul
Issue Date
1994-04
Type
Article
Language
Keywords
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Abstract
In this paper we present a complete design and implementation of a CMOS cell library which supports a formal high level synthesis framework. The library contains the logic level models and VLSI layouts of all primitive functions of the Realization Specification Language (RSL) [l] as well as some commonly used functions which are also built using these basic functions. Modular design methodology is employed to support the expandibility of the basic cells. Example of a formal matrix-matrix multiplier is presented to illustrate the application of the cell library.