Dual Slope ADC Design from Power, Speed and Area Perspectives
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Authors
Macwan, Isaac
Xiong, Xingguo
Hmurcik, Lawrence V.
Issue Date
2009
Type
Article
Language
en_US
Keywords
Engineering , Analog to digital converters
Alternative Title
Abstract
The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. In this paper, the design optimization of a 8-bit dual-slope ADC from power, speed and area perspectives is proposed. The proposed ADC consists of an analog part (including an integrator and a comparator) and a digital part (including a controller, counter and 8-bit register). Both D and T flip-flops are utilized in the ADC design to demonstrate its influence on area, performance (speed) and power by using different types of flip-flops. The layout of the ADC is designed with Mentor Graphics IC Station. The netlisted is extracted from the layout to include the parasitic capacitances for a more accurate power analysis. PSPICE power simulation is performed to read the power consumption of the ADC for the given inputs. Some efforts on reducing the power consumption of the ADC are also made. For example, the clock signal feeding to the flip-flops is revised to be data dependent so that the clock may be disabled to avoid unnecessary switches whenever it is possible. In this way, the overall power consumption of the ADC is reduced. Double-edge triggered (DET) flip-flops are also used in register circuitry. Since the DET flip-flops trigger at both the rising and falling edges, the clock signal is utilized to the fullest. The proposed dualslope ADC can be used for applications requiring an optimum chip area, minimum power consumption and excellent performance.
Description
© ASEE 2009
Citation
Publisher
ASEE