Implementation of a CMOS Wallace-tree Multiplier
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Authors
Li, Xiaoping
Issue Date
2009-04-03
Type
Article
Language
en_US
Keywords
Engineering , Computer science , Very-large-scale integration (VLSI) , Wallace-tree multiplier
Alternative Title
Abstract
As slow and expensive operation units, multipliers are often the bottleneck limiting the overall performance of many computational VLSI circuits. Various CMOS multiplier architectures are available, such as the array multiplier, carry-save multiplier, and Wallace-tree multiplier. Wallace-tree multiplier has been a very popular design due to its fast speed, ease for modularization and fabrication. In this paper, the design and simulation of an 8-bit Wallace-tree multiplier with PSPICE is proposed. In order for comparison, an 8-bit CMOS array multiplier is also designed. The worst-case delay of both multiplier architectures are extracted and Wallace-tree multiplier demonstrates significant speed enhancement compared to CMOS array multiplier. Some efforts are made to further improve the performance of Wallace-tree multiplier. The revision in the circuit structure demonstrates effective speed improvement for the Wallace-tree multiplier.
Description
© ASEE 2009
Citation
Publisher
ASEE